Integrated circuits are designed to operate under a variety of environmental conditions. To ensure that an integrated circuit operates correctly prior to packaging, the integrated circuit is coupled to a test system for testing. A test system often includes a custom designed space transformer that is implemented at wafer level test for electrical testing of products before packaging. As multi-chip modules become more mainstream, it becomes critical to enable as much content during this test step so that a bare die test can be achieved. Bare die tests may include, but are not limited to wafer or die level functional or structural test and known good die test. The space transformer plays a key role in enabling bare die test.
FIG. 1 illustrates an exemplary electrical test system. In the test system, electrical currents are applied to die bumps using miniature needles that are mechanically attached to the space transformer. The space transformer includes routing that translates the die bump pitch to a much wider contact pitch that can be mated with the tester motherboard.
Conventional space transformer solutions include several routing and power layers in order to provide the necessary test stimulus to the die. The test signals are routed through many interconnects, such as thin film vias, thin film transmission lines, ceramic vias, interposers, and motherboard routing. This routing establishes electrical contact between the dice and the tester, which allows direct electrical testing. As the packaging technologies trend toward multi-chip modules, where multiple chips are attached to the same package, several complications arise for testing.
First, the devices under test (DUT) are designed to interact with integrated circuits (ICs) that share the same package. This enables the designers to simplify the buffer designs, which lead to several design optimizations. For example, when a chipset is mounted on the same package as the CPU, the drivers on the CPU can be designed so they require much smaller die area, which leads to power and cost reduction. However for test, these circuits need to be routed to the tester for electrical test. The electrical routing length can be significantly longer than the drive capabilities of the circuits, which limits the test capabilities.
In addition, multi-chip packaging allows much denser input/output (I/O) on die to communicate with peripheral chips. Using the traditional test approaches, all of these additional I/Os need to be tested, which complicates the routing on the space transformer and require additional test resources.